b0VIM 8.1?y_:Rlaforestscriptor~laforest/public_html/fpga/CDC_Word_Synchronizer.vutf-8 3210#"! UtpAaBk(ad )AVL r # W V  @ 3 V   H Tl 6I)(  va`*Ls)(// and so cannot happen, and takes the more common 2 to 3 cycles. See the// take one cycle, is naturally reversed when crossing in the other direction,// sending/receiving clock edges that makes a CDC crossing in one direction// either direction are mutually exclusive. The timing of the// **\*Corner Case:** The situations where the CDC transfers take 1 cycle in//
// * 1**\*** to 3 sending cycles to do the CDC into the sending clock domain (and maybe complete a sending handshake)// * 1 receiving cycle to transform the completion of the receiving handshake to a level toggle// * 1**\*** to 3 receiving cycles to do the CDC into the receiving clock domain (and maybe complete a receiving handshake)// * 1 sending cycle to transform the completion of a sending handshake to a level toggle// cycles, in order:// relative sending and receiving clock frequencies, but we can count the// The absolute latency from sending to receiving handshake depends on the//## Latency and Throughput// FIFO depth/width, etc...// The value of `FIFO_BUFFER_RAMSTYLE` will depend on your device, CAD tool,// blocking. Use this if the downstream pipeline takes in data in bursts.// which allows `FIFO_BUFFER_DEPTH` sending handshakes to complete before// * '"FIFO"': Uses a [Pipeline FIFO Buffer](./Pipeline_FIFO_Buffer.html),// completes. Use this to allow both ends to send/receive data concurrently.// sending handshakes are blocked until the first receiving handshake// arrives before the first receiving handshake completes, then further// handshake completes. If the transfer from the next sending handshake// which allows the next sending handshake to start before the receiving// * '"SKID"': Uses a [Pipeline Skid Buffer](./Pipeline_Skid_Buffer.html),// to force the processing rate of the sender to match that of the receiver.// completes. Use this when sampling a changing signal (e.g.: a counter) or// and will not start the next sending handshake until the receiving handshake// * '"HALF"': Uses a [Pipeline Half Buffer](./Pipeline_Half_Buffer.html),// the receiving handshake:// * Set `OUTPUT_BUFFER_TYPE` to match the desired behaviour at the output of// `receiving_clock`.*// register. *This takes 3 cycles in both `sending_clock` and// to let any level toggle pass through CDC and reach its destination toggle// `receiving_clear` with a (preferably) synchronous reset signal long enough// * If a reset happens, you must assert both `sending_clear` and// problems.// a register, so you can sample synchronously changing inputs without// * When a sending handshake completes, `sending_data` is latched into//## Operating Notes// Synchronizer](./CDC_Pulse_Synchronizer_2phase.html).// This module is closely related to the [2-phase Pulse// sending handshake if there is more data to send.// which passes through CDC back into the sending clock domain to start a new// the receiving handshake completes, we convert that event into a level,// into the receiving clock domain and completes the receiving handshake. Once// convert a signal for new valid data into a level, which passes through CDC// The code is laid out in transfer order: we start at the sending handshake,// (consult your vendor datasheets regarding metastability).// `EXTRA_CDC_DEPTH` if you are running near the limits of your silicon// `sending_ready` and tie `receiving_ready` high. Add// short-circuited for continuous transfers without backpressure: ignore// handshakes at the sending and receiving ends, but these can be// another, regardless of relative clock frequencies. Uses ready/valid// Synchronizes the transfer of a word of data from one clock domain to//# CDC Word Synchronizerad u (]VUmgVP# 7 S %  v u t endmodule ); .pulse_anyedge_out (accept_next_word) // verilator lint_on PINCONNECTEMPTY .pulse_negedge_out (), .pulse_posedge_out (), // verilator lint_off PINCONNECTEMPTY .level_in (receiving_handshake_synced), .clock (sending_clock), ( convert_async_handshake_receiving Pulse_Generator// a pulse to start or complete the next sending handshake.// Finally, convert the synchronized receiving handshake completion into//## And Back to the Sending Handshake ); .bit_out (receiving_handshake_synced) .bit_in (receiving_handshake_toggle), .receiving_clock (sending_clock), ( into_sending ) .EXTRA_DEPTH (EXTRA_CDC_DEPTH) // Must be 0 or greater #( CDC_Bit_Synchronizer wire receiving_handshake_synced;// domain.// Then we synchronize the end of the 2-phase handshake into the sending clock ); .data_out (receiving_handshake_toggle) .data_in (receiving_handshake_toggle), .toggle (receiving_handshake_complete),