Portably Gating Signals

from FPGA Resources by GateForge Consulting Ltd.

A common situation is having to clear a signal to zero, to "annul" it, based on some other condition. For combinational logic, an AND gate can do that, and registers often have a synchronous or asynchronous clear input.

However, a bare AND gate in the source code often manifests in the RTL diagram as a mess of individual AND gates which obscure the schematic, and using the sync/async clear input to a register complicates synthesis: it might not be portable, might require specific source code to correctly infer, and may interfere with retiming and optimizations. These cases all depend on which CAD tool you use.

Instead, we can use an Annuller module, which encaspulates an AND gate of arbitrary width. This keeps the RTL diagram clean, conveys intent more clearly, and will be portable. This solution will not use the sync/async clear on registers, but on the other hand, will optimize itself into surrounding logic easily, which minimizes any additional delay.

// Annuls a value (gates it to zero)

`default_nettype none

module Annuller
    parameter       WORD_WIDTH         = 0
    input   wire                       annul,
    input   wire    [WORD_WIDTH-1:0]   in,
    output  reg     [WORD_WIDTH-1:0]   out

    localparam ZERO = {WORD_WIDTH{1'b0}};

    initial begin
        out = 0;

    always @(*) begin
        out <= (annul == 1'b1) ? ZERO : in;