The memory controller only reads/writes blocks of data. The data MUST be in MEM_DATA_WIDTH blocks and the address MUST be aligned to MEM_DATA_WIDTH lengths. Basically, the DDR is accessed as a block-oriented device and any address/data translation must be done in software.
The memory controller will accept an operation on a ready/valid interface, keep ready low while operating, and raise ready once the data transfer is complete.
localparam MEM_CTRL_OP_WIDTH = 1;
localparam [MEM_CTRL_OP_WIDTH-1:0] MEM_CTRL_OP_WRITE = 'd0; // Write a given number of MEM_DATA_WIDTH blocks starting at a MEM_DATA_WIDTH-aligned address (incrementing).
localparam [MEM_CTRL_OP_WIDTH-1:0] MEM_CTRL_OP_READ = 'd1; // Read a given number of MEM_DATA_WIDTH blocks starting at a MEM_DATA_WIDTH-aligned address (incrementing).