License

Unless explicitly stated otherwise, the entire contents of this book ("FPGA Design Elements") falls under the MIT License:

Copyright (c) 2019 Charles Eric LaForest, PhD.

Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

Hopefully, this license should be straightforward to get past your manager or legal team.

Disclaimer

It's simply not possible for a single person to write and test and exhaustively verify all the code in this book, and still get anything done. Thus, the state of the code and guidelines in this book ranges from "it should work, in theory" to "actively used in commercial applications". Use at your own risk.

That said, each design element is rather small and easy to manually inspect, and checked with a few basic tools. The Verilog source is run through the Verilator linter to find mistakes, and then through the Intel Quartus Prime CAD tool to find any elaboration and synthesis issues. Some more complex designs are further simulated using one of Verilator, Icarus Verilog, or Xilinx XSim.

If you do find any bugs, please accept my apologies, and do let me know so I can fix them. (Or better yet, please share your fix so I can include it here.)


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