FPGA Design Elements

Charles Eric LaForest, PhD.
GateForge Consulting, Ltd.

This is a continually evolving document. Please email any feedback to eric@fpgacpu.ca or Twitter @elaforest or join the Discord server.

Introduction

References

Tools

Useful Functions

Simulation and Test Bench

Input/Output

Boolean Logic

Synchronous Logic

Integer Arithmetic

Pulse Logic

Elastic Pipelines

Arbitration and Synchronization

Clock Domain Crossing (CDC)

Interfaces

Analog Signal Handling

Hashing and Pattern Matching

Communications

Miscellaneous Bits


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