FPGA Design Elements

Charles Eric LaForest, PhD.
GateForge Consulting, Ltd.

This is a continually evolving document. Please email any feedback to eric@fpgacpu.ca or Twitter @elaforest or join the Discord server.

Introduction

Simulation, Test Bench, and Other Miscellany

Input/Output

Boolean Logic

Synchronous Logic

Integer Arithmetic

Elastic Pipelines

Arbitration

Clock Domain Crossing

Interfaces

Analog Signal Handling

Communications

Appendices


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