Here are resources and technical articles aimed at FPGAs, derived from our experiences here at GateForge Consulting Ltd.
- HDL References
Because most info online about Verilog and VHDL doesn't get past the baby-steps, here's a collection of solid references.
- FPGA-Related Links
Links to resources by other people, high and low level.
- Verilog Coding Standard
Most of the difficulty with Verilog programming comes from programming
practice, and goes away with a certain coding style, which I describe here.
- System Design Standard
Most of the difficulty in FPGA system design comes from a lack of
modularity, not having a library of building blocks, and from not using the
logic optimization work done by the CAD tool to simplify design.
- Using Altera's USB-Blaster on Debian Linux
Most instructions are for Ubuntu, which has a significant difference, so here they are for plain Debian.
- Simulation/Synthesis Mismatch and the Design of Multiplexers
The limitations of Verilog
if/case statements leads to an alternative multiplexer design.
- Zero-Overhead Memory-Mapping Address Translation
We can translate non-power-of-two memory ranges and alignments back to a zero-based index without adding delay or area.
- Universal Address Decoders
Two simple, universal address decoders for static and dynamic address ranges, with minimal logic.
- Configurable Pipeline Delays
A useful module to align computations along a pipeline, and a basic registering idiom.
- Inferring On-Chip Memory
A generic module to infer on-chip FPGA Block RAMs (BRAMs), with parameterizable read-during-write behaviour.
- A Better Priority Arbiter
Extending Boolean operations with arithmetic gives a much simpler priority arbiter implementation.
- A Priority Thermometer Mask
A more complex example of extended Boolean operations, which returns a mask based on a one-hot bit vector.
- A Round-Robin Arbiter
A highly modular, single-cycle round-robin arbiter of parameterizable width.
- Portably Gating Signals
Placing a simple gating function into a module improves portability, RTL diagram readability, and conveys design intent.
- Universal Dyadic Boolean Operator
We can "transpose" a 4:1 multiplexer to efficiently and dynamically implement any of the 16 two-variable Boolean functions.
- Dual Triadic Boolean Operator
We can build a triadic operator out of dyadic operators, and extend it a bit for some flexibility and better data movement.
- Core/Instance/Adapter/Shim Architecture
A division of code for FPGA designs which improves portability and makes dealing with board-level problems a lot easier.
- Calculating All Condition Predicates
A very simple circuit can compute any arithmetic comparison predicate, and extends to compute most any other comparison.
- A Simple Master Reset
Rather than using a global reset, a few small counters can provide an orderly startup sequence and clean simulation.
- Pulse ↔ Level Conversions
Converting between pulses and levels can simplify some logic, and provides building blocks for more complex interfaces.
- Basic Clock Domain Crossing (CDC)
A Clock Domain Crossing synchronizer, and simple circuits for keeping a fast FPGA in sync with a slow peripheral.
- Designing A Skid Buffer
Pipelining handshake interfaces requires special logic, and is an useful example of datapath and FSM design.