FPGA Design Elements

Introduction

• Outline
• Licence and Disclaimer

Simulation, Test Bench, and Other Miscellany

• Ceiling of log₂(N) function
• Synthesis Harness Input
• Synthesis Harness Output
• Simulation Clock

Input/Output

• I/O Register
  • Single-Ended
  • Differential
• Regional Clock Buffer
• Global Clock Buffer
• I/O Bus Capture
• Signal Comparator (LVDS input)
• Debouncer (counter-based)
• Charlieplexer

Boolean Logic

• Constant
• Bit Reducer
• Annuller
• Word Reverser
• Word Reducer
• Bit Shifter
• Population Count
• Bit Voting
• Multiplexer (Binary, Behavioural)
• Multiplexer (Binary, Structural)
• Multiplexer (One-Hot)
• Demultiplexer (Binary)
• Address Decoder (Static)
• Address Decoder (Behavioural)
• Address Decoder (Arithmetic)
• Address Translator (Static)
• Address Translator (Arithmetic)
• Extended Boolean operations
  • Bitmask 0 Bit at Rightmost 1 Bit
  • Bitmask 1 Bit at Rightmost 0 Bit
  • Bitmask Isolate Rightmost 1 Bit
  • Bitmask Next with Constant Popcount
  • Bitmask Thermometer from Count
  • Bitmask Thermometer to Rightmost 0 Bit
  • Bitmask Thermometer to Rightmost 1 Bit
  • Bitmask Turn Off Trailing 1 Bits
  • Bitmask Turn On Trailing 0 Bits
  • Turn Off Rightmost 1 Bit
  • Turn Off Rightmost Contiguous 1 Bits
  • Turn Off Trailing 1 Bits
  • Turn On Rightmost 0 Bit
  • Turn On Trailing 0 Bits
• Universal Dyadic Operator
• Universal Triadic Operator
• Seven-segment Display Decoder (single BCD digit)

Synchronous Logic

• Register
• Register Pipeline
• Memory
  • Single-Port RAM (one read/write port)
  • Simple Dual-Port RAM (one read port, one write port)
  • True Dual-Port RAM (two read/write ports)
• Serial to Parallel Converter
• Parallel to Serial Converter
• Pulse Latch
• Pulse Generator
• Word Change Detector
• Bressenham Rate Converter
• Time Delay (cycles)
• Time Delay (fractions of seconds)
• Wall Clock
• Frequency Counter

Integer Arithmetic

• Adder/Subtractors
  • Binary
  • Binary (2-stage)
  • BCD
• Carry-In (Binary)
• Arithmetic Predicates (Binary)
• Up/Down Counters
  • Binary
  • BCD
  • Grey
  • One-Hot
  • Johnson
• Number Encoding Converters
  • Binary to One-Hot
  • One-Hot to Binary
  • Binary to Grey
  • Grey to Binary
  • Binary to Johnson
  • Johnson to Binary
  • General Shift-Add Converter (e.g. Binary to multi-digit BCD, or to H/M/S)
• Multiplier (Binary, parallel)
• Multiplier (BCD, parallel)
• Multiplier (Binary, iterative)
• Multiplier (BCD, iterative)
• Divider (Binary, parallel)
• Divider (BCD, parallel)
• Divider (Binary, iterative)
• Divider (BCD, iterative)
• Comparator
• Scaler
• Accumulators
  • Sum
  • Min
  • Max
  • Mean
  • Weighted Mean
• Zero-Crossing Detector
• Pseudo-Random Number Generators (PRNGs)
  • Linear Feedback (Fibonacci)
  • Linear Feedback (Xorshift family)
  • combinations of above...

Elastic Pipelines

• Skid Buffer
• FIFO
• Ready/Valid Fork (Lazy)
• Ready/Valid Fork (Eager)
• Ready/Valid Join
• Ready/Valid Branch
• Ready/Valid Merge

Arbitration

• Priority Encoder
• Priority Arbiter
• Round-Robin Arbiter
• Matrix Arbiter

Clock Domain Crossing

• CDC Synchronizer
• CDC Synchronizer (optimized for slow clock)
• CDC Pulse Synchronizer (Fast to Slow)
• CDC FIFO

Interfaces

• Key Encoder (NxM, no rollover)
• Quadrature Decoder
• Stepper Motor Driver
• Servo Motor Driver
• Basic I2C (just enough to read/write one address upon a trigger)
• Basic UART (no flow-control, no FIFO, fixed rate via parameter, enough to receive simple commands, or dump data)
• Basic NeoPixel Driver (really another kind of UART)

Analog Signal Handling

• Basic waveform generator (table-driven)
• PWM driver (for sound, motor, LEDs)
• Sound sample player (simple DAC data, played as PWM?)
• Basic DAC (PMW and output to resistor ladder)
• Basic ADC (SAR using PWM DAC and LVDS input)
• Sound sample recorder (ADC + Memory)

Communications

• Clock encoding and recovery (e.g. NRZ, MFM, DM, etc... as in old magnetic storage)
• Basic LVDS/TMDS communication (like UART, building block for LCD control, HDMI, multi-FPGA design, serial wire mux)
• Pseudo-differential communication (slower, using regular pins)
• Single-wire communication (tri-state bidir pin, self-clocked like NeoPixel)
• Hamming Code Generator
• Hamming Code Checker (EDAC)
• CRC Generator
• CRC Checker
• 8b/10b Encoder
• 8b/10b Decoder

Appendices

• On The Implementation of Finite State Machines
• Open Design Questions
• Verilog Coding Standard
• System Design Standard
• Useful Links
• Useful Books
• Tools Used To Write This Book
• Using Altera's Intel's USB-Blaster on Debian Linux