FPGA Design Elements
Charles Eric LaForest, PhD.
GateForge Consulting, Ltd.
This is a continually evolving document. Please email any
feedback to email@example.com or Twitter @elaforest or join the Discord server.
- v2h.py, which converts commented Verilog files into
HTML files. Line comments (no block comments!) are processed as Markdown.
Thus, the web page doesn't get stale as the code evolves. You will need the CSS Style file to render everything the same, but it's
in the repository and quite simple.
- verilinter, which is a small script using Verilator and Icarus Verilog to lint Verilog-2001
files. This little tool catches a lot of simple and not so simple Verilog
mistakes and corner cases.
- generate_file_skeleton.py, which
outputs a skeleton Verilog file in the style used in this book. Takes no
arguments. Simply pipe the output to a new file or your text editor window.
- generate_instance.py, which generates
a quick-and-dirty module instance when given a filename containing a module
definition as a parameter. When code is highly modular, writing module
instances takes a large fraction of your writing time. This automates most of
the grunt work. Pipe the output to your text editor window. This is a quick
hack made to work only with the modules in this book.
- Intel Quartus Prime.
The CAD tool suite for Intel (ex-Altera) FPGAs. It's smaller and easier to run
than Xilinx Vivado, and produces excellent RTL-level and post-synthesis
diagrams, which are very useful for checking and debugging designs.
Simulation and Test Bench
- I/O Register
- Regional Clock Buffer
- Global Clock Buffer
- I/O Bus Capture
- Signal Comparator (LVDS input)
- Debouncer (Low Latency)
Arbitration and Synchronization
Clock Domain Crossing (CDC)
- Seven-segment Display Decoder (single BCD digit)
- Key Encoder (NxM, no rollover)
- Quadrature Decoder
- Stepper Motor Driver
- Servo Motor Driver
- Basic I2C (just enough to read/write one address upon a trigger)
- Basic UART (no flow-control, no FIFO, fixed rate via parameter, enough to receive simple commands, or dump data)
- Basic NeoPixel Driver (really another kind of UART)
Analog Signal Handling
- Basic waveform generator (table-driven)
- PWM driver (for sound, motor, LEDs)
- Sound sample player (simple DAC data, played as PWM?)
- Basic DAC (PMW and output to resistor ladder)
- Basic ADC (SAR using PWM DAC and LVDS input)
- Sound sample recorder (ADC + Memory)
Hashing and Pattern Matching
- Simple substring match
- Hash Functions (misc. TBD)
- Bloom or Cuckoo Filter
- Clock encoding and recovery (e.g. NRZ, MFM, DM, etc... as in old magnetic storage)
- Basic LVDS/TMDS communication (like UART, building block for LCD control, HDMI, multi-FPGA design, serial wire mux)
- Pseudo-differential communication (slower, using regular pins)
- Single-wire communication (tri-state bidir pin, self-clocked like NeoPixel)
- Hamming Code Generator
- Hamming Code Checker (EDAC)
- CRC Generator
- CRC Checker
- 8b/10b Encoder
- 8b/10b Decoder