As I write out design elements, some questions about how to design them open up. The following cases are to explore later, or for the designer to watch out for.
Implementing a universal multiplexer module (any number of inputs of a given width, using a binary selector) is straightforward using a Verilog vector part select. Implementing it using design elements first suggests using NOT-AND logic to select an input, which would require complex conditional generation of NOT gates in a Verilog generate block.
However, viewing the problem as one of address decoding, then one can use a much simpler generate loop to iterate over the range of selector values and instantiate a single address decoder module (which already exists) for each case, without any conditional logic. This approach also generalizes the original vector part select design since we could use arbitrary, non-consecutive sets of selector values by passing them as a concatenation in a parameter.
This latter approach also removes the need for Verilog-specific vector part selects, which would make the multiplexer design element portable across HDLs.
There seems to be different ways to infer a synchronous reset for FPGA flip-flops: using an AND gate to zero the output results in separate logic, while using a multiplexer to select a zero output results in using the built-in synchronous reset of the flip-flop. This appears to be simple pattern matching by the synthesis tool. Either approach is desirable depending on the design, and can be encapsulated and made explicit by the Register design element.