References and Reading List

Here are the sources I've used while writing the FPGA Design Elements, covering digital design, bit manipulation, elastic pipelines, and clock-domain crossing.

Digital Design

• Design Books

  • Most books about digital design repeat the same superficial basics, and are usually out-of-print, out-of-date, and overpriced. The exception is Digital Design Principles and Practices by John F. Wakerly, which covers many topics effectively, and deals with real-life details at all levels, from microelectronics to coding practices. It also discusses number systems better than other textbooks.
  • Another useful book is "Logical Effort: Designing Fast CMOS Circuits" by Ivan Sutherland, Bob Sproull, and David Harris. It describes the relationships between the source/load capacitances and drive strengths of CMOS circuits in a simple and very structured way, allowing you to optimize and compare the delay of different circuit implementations pretty much using pencil-and-paper level mathematics. You can read a summary of Logical Effort Theory and an example of its application in one of my old project reports: Optimization Of Burst-Mode Circuits Using Logical Effort Theory.
  • The original VLSI book, "Introduction To VLSI Systems", by Carver Mead and Lynn Conway, is still worth looking through even though it describes obsolete NMOS technology with lamba-based design rules, because of its illuminating perspective (and beautiful full-color circuit layouts). It's the book that made me understand that capacitance is necessary for digital circuits to operate at all! The chapter on self-timed circuits is still one of the fundamental texts on asynchronous circuits.

• Finite State Machines

  Two books which I've found talk usefully about FSM design and implementation are:

  • "FSM-based Digital Design using the Verilog HDL" by Elliott Mins
  • "Finite State Machine Datapath Design, Optimization, and Implementation" by Reese Davis

• Arbiters

  There isn't much written about arbiters out there that isn't specializations of existing designs for particular uses. I couldn't find any good treatment of the fundamentals, and some ASIC arbiter designs rely on combinational loops, which are not allowed in conventional synchronous design. Here's what I could find:

  • "Principles and Practices of Interconnection Networks" by Dally and Towles, specifically Chapter 18, "Arbitration". This is also the major text on Network-on-Chip design.
  • "Microarchitecture of Network-on-Chip Routers" by Dimitrakopoulos, Psarras, and Seitanidis, specifically Chapter 4, "Arbitration Logic".
  • "Scalable arbiters and multiplexers for on-FPGA interconnection networks" by Dimitrakopoulos, Psarras, and Seitanidis, published at FPL 2011.
  • "Arbiters: Design Ideas and Coding Styles" by Matt Weber, published at SNUG Boston 2001. This is the most accessible source material for priority and round-robin arbiter design.
  • The Bitmask: Isolate Rightmost 1 Bit module efficiently implements a Priority Arbiter using adder carry-chain logic.

• Resets

  Ken Chapman's Get Smart About Reset: Think Local, Not Global discusses why, on FPGAs, it's important to minimize the number of registers receiving a reset signal, and to instead use the built-in register initialization at configuration or to architect the system to eventually get to a consistent state after a minimal reset.

• Flancter

  Rob Weinstein's Flancter is a clever little circuit which allows you to set a bit in one clock domain, and clear it from another clock domain without using an asynchronous reset or even having access to the setting clock domain. It needs supporting circuitry to be useful (e.g.: at least one CDC Bit Synchronizer), and you will have to carefully instruct your CAD tool on how to analyze the timing and set min/max delays on the two signals which cross clock domains without synchronization, and design your control circuitry to keep the set/reset signals mutually exclusive. That said, it's amazing for some advanced use cases, such as counting very fast and asynchronous sensor pulses. However, in most cases, you can get the same functionality with simpler CDC behaviour by using a CDC Flag Bit.

  (Thanks to Eric Smith (@brouhaha) for allowing me to host a copy of the hard-to-find original Flancter App Note, originally from his Floobydust page.)

• Hacker's Delight, 2nd ed., 2013, Henry S. Warren, Jr. This book covers algorithms related to bit manipulation, arithmetic, branch-free code, and other deep topics. A must-have for hardware designers. The website, which has extra material and errata, has since gone down, so this is an Archive.org link.
• Introduction to Low Level Bit Hacks provides a detailed explanation of the fundamental bit manipulations from which most others are built. (See: Hacker's Delight, Chapter 2, "Basics").
• Bit Twiddling Hacks is another repository of bit manipulation algorithms, complementing Hacker's Delight.
• The Aggregate Magic Algorithms has a few different algorithms, and notably, SWAR (SIMD Within A Register).
• the bit twiddler lists some C code, with cycle counts, explanations, and assembly output.
• Programming pages of Jasper Neumann. Detailed explanations with beautiful diagrams.
• awesome-bits by Keon Kim. Some nifty string and float algorithms here.
• The defunct (thus the archive.org links) Chess Programming Wiki describes 64-bit Bitboards, used to represent chess boards, which lend themselves to a rich discussion of various bit algorithms and their implementations:
  • General Setwise Operations
  • Bit Twiddling
  • Population count
  • BitScan
  • Flipping Mirroring and Rotating

The following papers are mainly useful for background and for implementation guides to pipeline branches, joins, forks, etc... Note however that in the academic literature, elastic pipelines are often expressed as valid/stop handshakes, rather than valid/ready handshakes, where "stop" is the inverse of "ready". This means parts of the diagrams have inverted logic from what it would be in valid/ready handshakes. Also, watch out for combinational paths, which aren't completely avoided in these designs: use Skid Buffers as necessary.

• R. T. Possignolo, E. Ebrahimi, H. Skinner and J. Renau, Fluid Pipelines: Elastic Circuitry meets Out-of-Order Execution, 2016 IEEE 34th International Conference on Computer Design (ICCD), Scottsdale, AZ, 2016, pp. 233-240, doi: 10.1109/ICCD.2016.7753285
• J. Cortadella, M. Kishinevsky, and B. Grundmann, SELF: Specification and design of synchronous elastic circuits, TAU ’06: Proceedings of the ACM/IEEE International Workshop on Timing Issues
• M. Abbas and V. Betz, Latency Insensitive Design Styles for FPGAs, 2018 28th International Conference on Field Programmable Logic and Applications (FPL), Dublin, 2018, pp. 360-3607, doi: 10.1109/FPL.2018.00068

• Clifford E. Cummings, Don Mills, and Steve Golson, Asynchronous & Synchronous Reset Design Techniques - Part Deux, SNUG 2003, Boston
• Clifford E. Cummings, Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog, SNUG 2008, Boston
• Clifford E. Cummings, Simulation and Synthesis Techniques for Asynchronous FIFO Design, SNUG 2002, San Jose