Tools Used To Write This Book

• v2h.py, which converts commented Verilog files into HTML files. Comments are processed as Markdown. Thus, the web page doesn't get stale as the code evolves.
• verilinter, which is a small script using Verilator and Icarus Verilog to lint Verilog-2001 files. This little tool catches a lot of simple and not so simple Verilog mistakes and corner cases.
• Intel Quartus Prime. The CAD tool suite for Intel (ex-Altera) FPGAs. It's smaller and easier to run than Xilinx Vivado, and produces excellent post-elaboration and post-synthesis diagrams, which are very useful for debugging designs.
• The particular look-and-feel of this site comes from the style.css file. It's pretty basic, but makes sure all pages look the same on pretty much any browser.