v2h.py, which converts commented Verilog files into
HTML files. Line comments (no block comments!) are processed as Markdown.
Thus, the web page doesn't get stale as the code evolves. You will need the CSS Style file to render everything the same, but it's
in the repository and quite simple.
verilinter, which is a small script using Verilator and Icarus Verilog to lint Verilog-2001
files. This little tool catches a lot of simple and not so simple Verilog
mistakes and corner cases.
generate_file_skeleton.py, which
outputs a skeleton Verilog file in the style used in this book. Takes no
arguments. Simply pipe the output to a new file or your text editor window.
generate_instance.py, which generates
a quick-and-dirty module instance when given a filename containing a module
definition as a parameter. When code is highly modular, writing module
instances takes a large fraction of your writing time. This automates most of
the grunt work. Pipe the output to your text editor window. This is a quick
hack made to work only with the modules in this book.
generate_fusesoc_core_file,
which generates a local core file for
FuseSoC, the award-winning
package manager and set of build tools for HDL code. This allows you to
integrate the FPGA Design Elements into your FuseSoC projects.
Intel Quartus Prime.
The CAD tool suite for Intel (ex-Altera) FPGAs. It's smaller and easier to run
than Xilinx Vivado, and produces excellent RTL-level and post-synthesis
diagrams, which are very useful for checking and debugging designs.