Multi-Ported Memories for FPGAs
As FPGAs increase in size, designers use them to build larger
systems-on-chip that require frequent data sharing, communication, queueing,
and synchronization among distributed functional units. These features boil
down to FIFOs and register files, which we can implement using multi-ported
This page indexes research about multi-ported memories, with the
most recent publications listed first.
Please direct any questions, corrections, or additions to
Charles Eric LaForest at email@example.com.
- Composing Multi-Ported Memories on FPGAs
Charles Eric LaForest, Zimo Li, Tristan O'Rourke, Ming G. Liu, J. Gregory Steffan
ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 7, Issue 3, Article 16, September 2014. (ACM page)
Updates the LVT and XOR papers, adds Xilinx implementation results, as well as more exploration of bi-directional LVT-based multi-ported memories.
- Application specific multi-port memory customization in FPGAs
Gorker Alp Malazgirt, Hasan Erdem Yantir, Arda Yurdakul, Smail Niar
IEEE International Conference on Field Programmable Logic and Applications (FPL), September 2014
Presents a fully automated methodology to tailor multi-port memories for a given application.
- An Efficient Heterogeneous Register File Implementation for FPGAs
Hasan Erdem Yantir, Arda Yurdakul
IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), May 2014
Explores heterogeneous, multi-pumped multi-ported memory implementations.
- Area Efficient Multi-Ported Memories with Write Conflict Resolution
Akshata Muddebihal, MS Thesis, University of Cincinnati, April 2014
Combines pure-multipumped memory banks with LVT to save logic and SRAM area, explores varying read/write port ratios, and adds conflict detection and resolution methods (a phantom bank, and port priority).
- Modular Multi-ported SRAM-based Memories
Ameer M.S. Abdelhadi and
Guy G.F. Lemieux
ACM International Symposium on Field-Programmable Gate Arrays (FPGA), February 2014, Monterey, CA. (ACM Page)
Generalizes LVT and XOR designs into an invalidation-based Live Value Table (I-LVT), using either XOR cancellation or a novel thermometer one-hot coding, yielding smaller and faster designs. Also formally characterizes the resource usage of various multi-ported memory designs.
- A Systematic Approach for Register File Design in FPGAs
Hasan Erdem Yantir's M.Sc. Thesis
Explores the design space of heterogeneous register files on FPGAs. See the two papers above too.
- Efficient Implementations of Multi-pumped Multi-port Register Files in FPGAs
Hasan Erdem Yantir, Salih Bayar, Arda Yurdakul
Euromicro Conference on Digital System Design (DSD), September 2013
Improves the performance of multi-pumped memories by using shift registers instead of multiplexers at the read/write ports.
- DESIGN CHOICES OF MULTI-PORTED MEMORY FOR FPGA
Hoang Trang, Ho Chi Minh City University of Technology
Journal of Science and Technology (JST) (Special Information and Communication Technology edition (JICT)), Le Quy Don University, Number 2, April 2013
Multi-pumps the LVT and adds contention resolution, to improve speed and reduce area of conventional LVT multi-ported memories.
- Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems
Jongsok Choi, Kevin Nam, Andrew Canis, Jason Anderson, Stephen Brown, and Tomasz Czajkowski
IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 17-24, Toronto, Canada, April 2012.
Introduces multi-pumped and LVT-based multi-ported memories with bi-directional read/write ports. They use these to implement processor caches.
- Multi-Ported Memories for FPGAs via XOR
Charles Eric LaForest, Ming G. Liu, Emma Rae Rapati, and J. Gregory Steffan
ACM International Symposium on Field-Programmable Gate Arrays (FPGA), February 2012, Monterey, CA. (ACM Page)
Uses XOR cancellation to reconstruct the most-recently written data amongst multiple memory banks. Another form of true multi-ported memory.
- CRAM: Coded Registers for Amplified Multiporting
Vignyan Reddy Kothinti Naresh, David J. Palframan, Mikko H. Lipasti
IEEE/ACM International Symposium on Microarchitecture (MICRO-44), 2011
Not an FPGA implementation, but shows an alternative form of XOR coding for multi-ported register files in superscalar processors.
- A Multiported Register File with Register Renaming for Configurable Softcore VLIW Processors
Fakhar Anjam, Stephan Wong, and Faisal Nadeem
A VLIW Softcore Processor with Dynamically Adjustable Issue-slots
Fakhar Anjam, Muhammad Nadeem, and Stephan Wong
IEEE International Conference on Field-Programmable Technology (FPT), December 2010, Beijing.
Two papers showing how to use register-renaming to avoid needing an LVT, saving power and area, and a modified LVT multi-ported memory configurable as a single 4w8r or dual 2w4r memories.
- Efficient Multi-Ported Memories for FPGAs
Charles Eric LaForest and J. Gregory Steffan
ACM International Symposium on Field-Programmable Gate Arrays (FPGA), February 2010, Monterey, CA. (ACM Page)
Introduces the Live Value Table (LVT), which coordinates multiple banks of memory into a true multi-ported memory.
- A Configurable Multi-Ported Register File Architecture for Soft Processor Cores
Mazen A. R. Saghir and Rawan Naous
International Workshop on Applied Reconfigurable Computing (ARC 2007), pp. 14-25, Springer-Verlag LNCS 4419, March 27-29, 2007.
Early research on banked and replicated multi-ported memories.
- Advanced Synthesis Cookbook
Altera's July 2009 (now updated to 2011) Advanced Synthesis Cookbook describes a 1-bit flag to get a quad-port memory out of dual-port memories. See page 60.
- Design issues for prototype implementation of a pipelined superscalar processor in programmable logic
IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM), volume 1, pages 155-158 vol.1, Aug. 2003.
Multipumps memories by performing reads and writes on consecutive rising and falling clock edges within a processor cycle.
- Implementing Multi-Port Memories in ProASICPLUS Devices
Actel's July 2003 Application Note AC176 describes a multi-pumped memory block to get dual or quad ports.
- Quad-Port Memories in Virtex Devices
Nick Sawyer and Marc Defossez
Xilinx's September 2002 Application Note XAPP228 describes a multi-pumped memory block to get quad ports.
- The Myriad Uses of Block RAM
www.fpgacpu.org, October 1998
Large list of the many potential applications of the then new FPGA Block RAMs. Predicts many forms of multi-ported memory (multi-pumped, banked, replicated, LVT).