GateForge Consulting Ltd.
Custom FPGA logic design and software development services.
Our main strengths are high-speed custom logic design and system
integration. For example, we integrated into a 500 MHz Virtex Ultrascale+
platform a real-time video processing IP, a ML accelerator for object
recognition, multiple video codec IPs, multiple DDR4 controllers, and AXI
interconnect. We also wrote the multi-core host software to communicate with
the system and process multiple raw 1080p30 video streams in parallel. We
follow a System Design Standard refined over
many projects.
We have over a decade of experience with Quartus, Vivado, and ISE for
consumer and industrial applications on Zynq devices, scientific
instrumentation on Kintex-7, space-rating validation on Spartan-6Q, ASIC
emulation on Virtex-7, image processing and system infrastructure on Artix-7,
and real-time video processing on Virtex UltraScale+ on Amazon's F1 cloud
service.
We mainly work in Verilog-2001, and take great effort in writing modular and
cleanly synthesizable code, following our in-house Verilog Coding Standard. You can see our library of FPGA Design Elements. We can also
deliver work in VHDL, and other HDLs as required by our clients.
We have almost 30 years of experience working in Linux environments,
spanning everything from system administration to kernel programming. In
software, we work in most any language, but primarily C, Python, assembly
(MIPS, ARM, 6502), and occasionally in Perl and Forth.
Contact
- gateforge@fpgacpu.ca
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Client Projects
- Audio/Video format conversion on Xilinx Zynq platform, and interfacing
to H.264 encoding hardware. Shipped to over 1000 customers.
- Redesign of high-speed ADC SERDES interfaces for a port from Spartan-6
to Kintex-7, improved with data frame self-alignment.
- Rebuild of SEU (Single Event Upset) test circuits from Virtex-5 to
Virtex-7, with new interfaces to legacy TID (Total Ionizing Dose) testing
hardware. These circuits are used to test FPGAs under proton and heavy ion
beam exposure.
- Implementation of space-rating test cases for defense-grade Spartan-6Q
devices. These tests reach the extremes of I/O standards, SERDES and PLL
operating ranges, pin leakage currents, and delays.
- Conversion of a set-top box video compositing product onto Amazon's F1
cloud FPGA platform, including FPGA floorplanning, build debug, and timing
closure, and creation of core application software and related AWS
infrastructure.
- Design and implementation of custom interfaces to multiple CPUs, DDR2
RAM, a camera, and custom AXI peripherals in a medical device. Board design
reviews to update system from Spartan-6 to Artix-7.
- Integration of video processing, ML acceleration, and video encoding
IPs on a Xilinx VCU1525 board, with custom-built AXI address re-mapping logic
to translate IP memory ranges.
- Debugging Closed Caption extraction from XDCAM video for a broadcasting platform.
- Updating a legacy industrial control EtherCAT interface from a proprietary
Spartan-6/TigerSHARC system to a dual-core Zynq device, with extensions to work
in a real-time dual-OS environment (PetaLinux and FreeRTOS).
- Design of custom control and data processing logic for industrial research
instrumentation, with specialized Network-on-Chip, high-precision (100+ bit)
integer processing pipeline, and host-side Python control software.
Internal Projects
- FPGA Design Elements
A reference library of fundamental (and advanced) digital logic design elements, along with standards for Verilog coding and system design. Think of it as a hardware analog to the C Standard Library ("libc") and its documentation.
- The Octavo Soft-Processor
Technology demonstrator. Open-Source soft-processor for high-performance, aimed at rapid FPGA system development.
GitHub repository
Publications
Some examples of past FPGA design research. You can find a complete list at the Publications page.
- Octavo: An FPGA-Centric Processor Family
Charles Eric LaForest and J. Gregory Steffan
ACM International Symposium on Field-Programmable Gate Arrays (FPGA), February 2012, Monterey
Using our own design techniques, we show it is possible to create very high-speed (500+MHz) soft-CPUs on FPGAs, along with fast I/O, memory, and multipliers.
- Composing Multi-Ported Memories on FPGAs
Charles Eric LaForest, Zimo Li, Tristan O'Rourke, Ming G. Liu, J. Gregory Steffan
ACM Transactions on Reconfigurable Technology and Systems (TRETS), August 2014, Volume 7, Issue 3, Article No. 16
We present a thorough exploration and evaluation of the design space of FPGA-based soft multi-ported memories for conventional solutions, and also for the recently-proposed Live Value Table (LVT) and XOR approaches to unidirectional-port memories, reporting results for both Altera and Xilinx FPGAs.
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