OCTAVO

The Octavo soft-processor is a research CPU aimed at building FPGA overlay architectures. Instead of implementing your whole design in hardware, and waiting hours for it to place-and-route after each change, you implement just the compute-heavy parts in hardware alongside an Octavo instance, and leave the rest to software. Most design cycles now reduce to quick compiles, and both the hardware and software design jobs are simplified. This isn't a new idea, but Octavo has higher software performance and couples more directly to external hardware than previous soft-processors.

Clock Frequency

Although Octavo was originally designed for Altera's Stratix IV FPGA, it performs pretty well on other Altera devices. It generally runs twice as fast as a NiosII/f, and gets pretty close to the absolute upper clock frequency limit allowed by the FPGA hardware. We could re-build Octavo for Xilinx devices, but the ALU would have to be done completely differently. See the works of Cheah, Fahmy, and Kapre on the iDEA soft-processor, and its pipelining and forwarding, for their high-performance solutions on Xilinx FPGAs.

Octavo Fmax on Various Altera Devices
FamilyDeviceAverageMaximumAvg/MaxLimitMax/Lim
  (MHz)(MHz)(Ratio)(MHz)(Ratio)
Stratix V 5SGXEA7N2F45C15085880.8646750.871
Stratix IV EP4S100G5H40I14704930.9535500.896
Arria V 5AGXFB5K4F40I32723000.9074000.750
Cyclone V 5CGXFC7D6F31C62392670.8953150.848
Cyclone IV EP4CGX30CF19C61871970.9493150.625

Architecture

Octavo's raw speed comes from an architecture adapted the to the underlying FPGA, so the trade-offs are different than for an ASIC. The architecture works best for parallel code, but the increased branching and addressing efficiency also helps sequential code. Octavo is more of a number-cruncher than a general-purpose processor.

Block Diagram

Octavo CPU Block Diagram

Publications

Download

You can get the complete source from the Octavo GitHub Repository, updated as work progresses.


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